Due to advancements in processing technology, complex integrated circuits (ICs) can be designed at various levels of abstraction. Using a hardware description language (HDL), circuits can be designed at the gate level, the register transfer level (RTL), and higher logical levels. When designing using an HDL, the design is often structured in a modular manner. The designer describes a module in terms of the behavior of a system, the behavior describing the generation and propagation of signals through combinatorial modules from one set of registers to another set of registers. HDLs provide a rich set of constructs to describe the functionality of a module. Modules may be combined and augmented to form even higher level modules.
Prior to implementation, an HDL design can be simulated to determine whether the design will function as required. Wasted manufacturing costs due to faulty design may thereby be avoided. Numerous tools are available for simulating circuit designs including, for example, high-level modeling systems (HLMS) and HDL simulators.
Simulation of an HDL design comprises a compilation phase and a runtime simulation phase. In the compilation phase, HDL source code is input, analyzed, and elaborated, to generate executable simulation code. In the runtime simulation phase, the code generated in the compilation phase is executed by a simulation engine to simulate the design.
From a user perspective, HDL simulators work by compiling the HDL design once, and then executing the compiled design many times during the runtime phase. Therefore, the runtime performance of HDL simulators is of critical importance, and may be more important than compile time performance.
An HDL design is a hierarchy of modules, whose behavior is described by means of HDL processes. When the HDL design is written in the VHDL language, an HDL process corresponds to either a VHDL process, a concurrent signal assignment, or a concurrent assertion. When the HDL design is written in the Verilog language, an HDL process corresponds to either a Verilog always block, or an initial block, or an assign statement, or a gate. Procedure calls may or may not be regarded as HDL processes.
From a hardware point of view, the HDL processes represent hardware that responds to changes in inputs. For example, a change to an output of one circuit may concurrently trigger responses in multiple circuits having inputs coupled to the output. However, due to the sequential nature of most software, the simulation of the processes representing the affected circuits usually takes place sequentially.
HDL simulators schedule execution of HDL statements such that global variables or signals input to the HDL statements are properly updated and race conditions between concurrent HDL statements are avoided. In VHDL, simulation of HDL processes is performed over a number of simulation cycles which may be either time advance cycles or delta cycles. A time advance cycle advances the simulation from a first time period of circuit operation being simulated to the next time period of circuit operation being simulated. A delta cycle is a simulation cycle in which the simulation time at the beginning of the cycle is the same as at the end of the cycle. That is, simulation time is not advanced in a delta cycle. For example, a delta cycle begins with updates to values of signals. Each update may trigger a number of processes which would be concurrently affected if implemented in hardware. The delta cycle ends after the triggered processes complete execution or are postponed by an event scheduling statement such as a wait statement. The HDL processes executed in a delta cycle may be executed in any order because time is not advanced and signals are not updated until the next simulation cycle.
In Verilog, simulation time slots are divided into multiple regions in which events can be scheduled, and the regions are referred to as event scheduling regions. HDL processes scheduled within an event scheduling region, may be executed concurrently in any arbitrary order. However, processes of different event scheduling regions must be scheduled in a correct order so that signals can be properly synchronized and dependencies accounted for.
While envisioned embodiments are applicable to either VHDL and Verilog, for ease of description, the example and embodiments are primarily described herein with reference to VHDL. Reference to a VHDL delta cycle is understood to also refer to an event scheduling region in the Verilog context.
Previous attempts to simulate the HDL processes in parallel using multiple processors may be computationally inefficient due to the costs of synchronizing and communicating between threads of execution. Improper load balancing may also reduce efficiency. Load balancing refers to the distribution of processing tasks among threads so that all threads are kept busy all of the time. If processors are assigned disproportionate amounts of work, the processors may finish assigned work at different times. As a result, one or more processors may remain idle after completing execution of the assigned processes in a simulation cycle while other processors have further work to perform. Previous attempts to simulate the HDL processes in parallel do not address the complexity of the tasks, which affects the time and resources necessary for simulation. Rather, the distribution and order of execution of processes in parallel at runtime is either arbitrary, or depends on the order in which processes were scheduled for execution. As a result, such approaches exhibited excessive synchronizing times caused by an excessive number of processing threads, and idle processing threads caused by inefficient load balancing.
One or more embodiments may address one or more of the above issues.